TimingDesigner* Library Files for 28F640J5

Intel Corp. (Folsom)

Architecture:
Type :
Last Update:

Flash Memory Components Intel(R) StrataFlash(TM) Memory
Timing Designer Models/Viewer
9/15/97 4:37:36 PM

Vendor Information

Tool Description:

Tool Features:

Device read/write timing models

Enables interface timing analysis in design

Ensures timing compatibility between memories, microprocessors, programmable logic, etc.

Runs under Chronology's TimingDesigner*/TimingViewer*

File Attachments:

640j5tmd.zip - led the 'create/restore directory structure' option.
tvwr3101.exe - After downloading TVWR3101.EXE to the destination directory, run this file to start the extraction process. Then to install, run INSTALL.EXE

Supported Device Detail Matrix:

Part & Package
Revision
Status

28F640J5 - SSOP-56 ld
28F640J5 - uBGA-56 ball
1.0
1.0
Released
Released

Vendor Information:

Intel Corp. (Folsom)

1900 Prairie City Road
Folsom , CA 95630
USA

Tech : (916) 356-3104
Email : flash@inside.intel.com
Fax : (916) 356-2803
Toll Free : (800) 628-8686
BBS : (916) 356-3600
URL : http://developer.intel.com

Contact the vendor above for the latest Distributor information

	Part & Package		Revision		Status
	28F640J5 - SSOP-56 ld 28F640J5 - uBGA-56 ball		1.0 1.0		Released Released